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19-1429; Rev 0; 2/99
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference
General Description
The MAX5130/MAX5131 are low-power, 13-bit, voltageoutput digital-to-analog converters (DACs) with an internal precision bandgap reference and output amplifier. The MAX5130 operates on a single +5V supply with an internal reference of +2.5V, and is capable of a +4.0955V full-scale output. If necessary, the user can override the on-chip, <10ppm/C voltage reference with an external reference. The MAX5131, operating on +3V, delivers its +2.04775V full-scale output with an internal precision reference of +1.25V. Both devices draw only 500A of supply current, which reduces to 3A in power-down mode. In addition, their power-up reset feature allows for a userselectable initial output state of either 0V or midscale and minimizes output voltage glitches during power-up. The serial interface is compatible with SPITM, QSPITM, and MICROWIRETM, which makes the MAX5130/MAX5131 suitable for cascading multiple devices. Each DAC has a double-buffered input organized as an input register followed by a DAC register. A 16-bit shift register loads data into the input register. The DAC register may be updated independently or simultaneously with the input register. Both devices are available in a 16-pin QSOP package and are specified for the extended-industrial (-40C to +85C) temperature range. For pin-compatible 14-bit upgrades, see the MAX5170/MAX5172 data sheet; for pin-compatible 12-bit versions, see the MAX5120/ MAX5121 data sheet. o Single-Supply Operation +5V (MAX5130) +3V (MAX5131) o Full-Scale Output Range +4.0955V (MAX5130) +2.04775V (MAX5131) o Built-In 10ppm/C (max) Precision Bandgap Reference +2.5V (MAX5130) +1.25V (MAX5131) o Adjustable Output Offset o SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial Interface o Pin-Programmable Shutdown Mode and PowerUp Reset (0V or Midscale Output Voltage) o Buffered Output Capable of Driving 5k || 100pF or 4-20mA Loads o Space-Saving 16-Pin QSOP Package o Pin-Compatible Upgrades to the 12-Bit MAX5120/MAX5121 o Pin-Compatible 14-Bit Upgrades Available (MAX5170/MAX5172)
Features
MAX5130/MAX5131
Applications
Industrial Process Control Automatic Test Equipment (ATE) Digital Offset and Gain Adjustment Motion Control P-Controlled Systems
Pin Configuration
TOP VIEW
OS 1 OUT 2 RSTVAL 3 PDL 4 CLR 5 CS 6 DIN 7 SCLK 8 16 VDD 15 REFADJ 14 REF
Ordering Information
PART MAX5130AEEE MAX5130BEEE MAX5131AEEE MAX5131BEEE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 16 QSOP 16 QSOP 16 QSOP 16 QSOP INL (LSB) 0.5 1 1 2
MAX5130 MAX5131
13 AGND 12 PD 11 UPO 10 DOUT 9 DGND
SPI and QSPI are trademarks of Motorola, Inc.
QSOP
MICROWIRE is a trademark of National Semiconductor Corp.
1
________________________________________________________________ Maxim Integrated Products
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND ...............................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs (DOUT, UPO) to DGND .....-0.3V to (VDD + 0.3V) OUT to AGND.............................................-0.3V to (VDD + 0.3V) OS to AGND ...................................(AGND - 4V) to (VDD + 0.3V) REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) QSOP (derate 8.00mW/C above +70C) .....................667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5130 (+5V)
(VDD = +5V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Gain Error Full-Scale Voltage Full-Scale Temperature Coefficient (Note 3) Power-Supply Rejection Ratio REFERENCE Output Voltage Output Voltage Temperature Coefficient Reference External Load Regulation Reference Short-Circuit Current REFADJ Current DIGITAL INPUT Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V VIH VIL VHYS IIN CIN VIN = 0 or VDD -1 200 0.001 8 1 3 0.8 V V mV A pF REFADJ = VDD VREF TCVREF VOUT/IOUT TA = +25C MAX5130A MAX5130B 0 IOUT 100A (sourcing) 2.5 16 24 0.1 4 3.3 7 1 V ppm/C V/A mA A N INL DNL VOS GE VFS TCVFS PSRR Code = 1FFF hex, TA = +25C MAX5130A MAX5130B 4.5V VDD 5.5V MAX5130A MAX5130B 13 -0.5 -1 -1 -10 -3 4.0463 -0.2 4.0955 3 10 20 0.5 1 1 10 3 4.1447 30 50 250 Bits LSB LSB mV mV V ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference
ELECTRICAL CHARACTERISTICS--MAX5130 (+5V) (continued)
(VDD = +5V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing (Note 4) OS Input Resistance Time Required to Exit Shutdown Digital Feedthrough POWER REQUIREMENTS Power-Supply Voltage (Note 5) Power-Supply Current (Note 5) Power-Supply Current in Shutdown VDD IDD ISHDN 4.5 500 3 5.5 600 20 V A A CS = VDD, fSCLK = 100kHz, VSCLK = 5Vp-p ROS 83 SR To 0.5LSB, VSTEP = 4V 0.6 20 0 to VDD 121 2 5 V/s s V k ms nV-s SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5130/MAX5131
ELECTRICAL CHARACTERISTICS--MAX5131 (+3V)
(VDD = +3V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Gain Error Full-Scale Voltage Full-Scale Temperature Coefficient (Note 3) Power-Supply Rejection Ratio REFERENCE Output Voltage Output Voltage Temperature Coefficient Reference External Load Regulation Reference Short-Circuit Current REFADJ Current DIGITAL INPUT Input High Voltage Input Low Voltage Input Hysteresis VIH VIL VHYS 200 2.2 0.8 V V mV REFADJ = VDD VREF TCVREF VOUT/IOUT TA = +25C MAX5131A MAX5131B 0 IOUT 100A (sourcing) 1.25 3 10 0.1 4 3.3 7 1 V ppm/C V/A mA A N INL DNL VOS GE VFS TCVFS PSRR RL = Data = 1FFF hex, TA = +25C MAX5131A MAX5131B 2.7V VDD 3.3V MAX5131A MAX5131B 13 -1 -2 -1 -10 -5 -0.2 3 10 20 1 2 1 10 5 10 30 250 Bits LSB LSB mV mV V ppm/C V/V SYMBOL CONDITIONS MIN TYP MAX UNITS
2.02317 2.04775 2.07232
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
ELECTRICAL CHARACTERISTICS--MAX5131 (+3V) (continued)
(VDD = +3V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Input Leakage Current Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Output Voltage Swing (Note 4) OS Input Resistance Time Required to Exit Shutdown Digital Feedthrough POWER REQUIREMENTS Power-Supply Voltage (Note 5) Power-Supply Current (Note 5) Power-Supply Current in Shutdown VDD IDD ISHDN 2.7 500 3 3.6 60 20 V A A CS = VDD, fSCLK = 100kHz, VSCLK = 3Vp-p ROS 83 SR To 0.5LSB, VSTEP = 2V 0.6 20 0 to VDD 121 2 5 V/s s V k ms nV-s VOH VOL ISOURCE = 2mA ISINK = 2mA VDD - 0.5 0.13 0.4 V V SYMBOL IIN CIN CONDITIONS VIN = 0 or VDD MIN -1 TYP 0.001 8 MAX 1 UNITS A pF
TIMING CHARACTERISTICS--MAX5130 (+5V)
(VDD = +5V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay Time SCLK Fall to DOUT Valid Propagation Delay Time SCLK Rise to CS Fall Delay Time CS Rise to SCLK Rise Hold Time CS Pulse Width High SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 40 100 CONDITIONS MIN 100 40 40 40 0 40 0 80 80 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference
TIMING CHARACTERISTICS--MAX5131 (+3V)
(VDD = +3V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SCLK Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time SDI Setup Time SDI Hold Time SCLK Rise to DOUT Valid Propagation Delay Time SCLK Fall to DOUT Valid Propagation Delay Time SCLK Rise to CS Fall Delay Time CS Rise to SCLK Rise Hold Time CS Pulse Width High SYMBOL tCP tCH tCL tCSS tCSH tDS tDH tDO1 tDO2 tCS0 tCS1 tCSW CLOAD = 200pF CLOAD = 200pF 10 75 150 CONDITIONS MIN 150 75 75 60 0 60 0 200 200 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
MAX5130/MAX5131
Note 1: Accuracy is guaranteed as shown in the following table: VDD (V) 5 3 Accuracy Guaranteed From Code: 20 40 To Code: 8191 8191
Note 2: Offset is measured at the code closest to 10mV. Note 3: The temperature coefficient is determined by the "box" method in which the maximum VOUT over the temperature range is divided by T. Note 4: Accuracy is better than 1.0LSB for VOUT = 10mV to (VDD - 180mV). Guaranteed by PSR test on end points. Note 5: RLOAD = and digital inputs are at either VDD or DGND.
Typical Operating Characteristics
(VDD = +5V (MAX5130), VDD = +3V (MAX5131), RL = 5k, CL = 100pF, OS = AGND, TA = +25C, unless otherwise noted.)
MAX5130 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5130/31 toc01
MAX5130 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
0.15 0.10 DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 2.490 0 2000 4000 6000 8000 10,000 -60 -40
MAX5130/31 toc02
MAX5130 REFERENCE VOLTAGE vs. TEMPERATURE
MAX5130/31 toc03
0.20 0.15 0.10 INL (LSB) 0.05 0 -0.05 -0.10 -0.15 -0.20 0 2000 4000 6000 8000
0.20
2.510
REFERENCE VOLTAGE (V)
2.505
2.500
2.495
10,000
-20
0
20
40
60
80
100
DIGITAL INPUT CODE
DIGITAL INPUT CODE
TEMPERATURE (C)
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5130), VDD = +3V (MAX5131), RL = 5k, CL = 100pF, OS = AGND, TA = +25C, unless otherwise noted.)
MAX5130 SUPPLY CURRENT vs. TEMPERATURE
MAX5130/31 toc04
MAX5130 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5130/31 toc05
MAX5130 SHUTDOWN CURRENT vs. TEMPERATURE
MAX5130/31 toc06
500 450 SUPPLY CURRENT (A) 400 (CODE = 1555 HEX) 350 300 250 200 -60 -40 -20 0 20 40 60 80 (CODE = 0000 HEX)
500
4.0 3.5 SHUTDOWN CURRENT (A) 3.0 2.5 2.0 1.5 1.0
450 SUPPLY CURRENT (A) (CODE = 1555 HEX) 400
350 (CODE = 0000 HEX)
300
250 100 4.0 4.5 5.0 5.5 6.0 TEMPERATURE (C) SUPPLY VOLTAGE (V)
-60
-40
-20
0
20
40
60
80
100
TEMPERATURE (C)
MAX5130 FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5130/31 toc07
MAX5130 FULL-SCALE ERROR vs. RESISTIVE LOAD
MAX5130/31 toc08
MAX5130 DYNAMIC RESPONSE RISE TIME
MAX5130/31-09
4.099 4.098 FULL-SCALE OUTPUT (V) 4.097 4.096 4.095 4.094 4.093 -60 -40 -20 0 20 40 60 80
0.5 0 FULL-SCALE ERROR (LSB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0
RL = 5k CL = 100pF
CS 5V/div
OUT 1V/div
100
0.1
1
10
100
5s/div
TEMPERATURE (C)
RESISTOR (k)
MAX5130 DYNAMIC RESPONSE FALL TIME
MAX5130/31-10
MAX5130 DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5130/31-11
MAX5130 MAJOR CARRY TRANSITION
MAX5130/31-12
CS 5V/div
SCLK 2V/div
CS 2V/div
OUT 1V/div OUT 1mV/div AC COUPLED
OUT 100mV/div AC COUPLED
5V/div
2s/div
5s/div
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5130), VDD = +3V (MAX5131), RL = 5k, CL = 100pF, OS = AGND, TA = +25C, unless otherwise noted.)
MAX5131 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5130/31 toc-13
MAX5130/MAX5131
MAX5131 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE
MAX5130/31 toc-14
MAX5131 REFERENCE VOLTAGE vs. TEMPERATURE
MAX5130/31 toc-15
0.3 0.2 0.1
0.25
1.250
INL (LSB)
0.05
REFERENCE VOLTAGE (V)
0.15
1.248
DNL (LSB)
1.246
0 -0.1 -0.2 -0.3 0 2000 4000 6000 8000 10,000 DIGITAL INPUT CODE
-0.05
1.244
-0.15
1.242
-0.25 0 2000 4000 6000 8000 10,000 DIGITAL INPUT CODE
1.240 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
MAX5131 SUPPLY CURRENT vs. TEMPERATURE
MAX5130/31 toc-16
MAX5131 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5130/31 toc-17
MAX5131 SHUTDOWN CURRENT vs. TEMPERATURE
MAX5130/31 toc-18
400 350 SUPPLY CURRENT (A) 300 250 200 150 100 -60 -40 -20 0 20 40 60 80 CODE = 1555 HEX
400 375 SUPPLY CURRENT (A) CODE = 1555 HEX 350 325 300 275 250 CODE = 0000 HEX
1.0
CODE = 0000 HEX
SHUTDOWN CURRENT (A)
0.8
0.6
0.4
0.2
0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 -60 -40 -20 0 20 40 60 80 100 SUPPLY VOLTAGE (V) TEMPERATURE (C)
100
TEMPERATURE (C)
MAX5131 FULL-SCALE OUTPUT vs. TEMPERATURE
MAX5130/31 toc-19
MAX5131 FULL-SCALE OUTPUT vs. RESISTIVE LOAD
MAX5130/31 toc-20
MAX5131 DYNAMIC RESPONSE RISE TIME
MAX5130/31-21
2.046 RL = 5k CL = 100pF
0.5
FULL-SCALE ERROR (LSB)
FULL-SCALE OUTPUT (V)
2.044
0
CS 2V/div
2.042
-0.5
2.040
2.038
-1.0
OUT 500mV/div
2.036 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
-1.5 0.1 1 10 100 2s/div RESISTOR (k)
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
Typical Operating Characteristics (continued)
(VDD = +5V (MAX5130), VDD = +3V (MAX5131), RL = 5k, CL = 100pF, OS = AGND, TA = +25C, unless otherwise noted.)
MAX5131 DYNAMIC RESPONSE FALL TIME
MAX5130/31-22
MAX5131 DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5130/31-23
MAX5131 MAJOR CARRY TRANSITION
MAX5130/31-24
CS 2V/div
SCLK 2V/div
CS 2V/div
OUT 500mV/div
OUT 500V/div AC COUPLED
OUT 100mV/div AC COUPLED
2s/div
2s/div
5s/div
Pin Description
PIN 1 2 3 NAME OS OUT RSTVAL Offset Adjust (Analog Input) Analog Output Voltage. High impedance if part is in shutdown. Reset Value Input (Digital Input) 1: Tie to VDD to select midscale as the output reset value. 0: Tie to DGND to select 0V as the output reset value. Power-Down Lockout (Digital Input) 1: Normal operation. 0: Disallows shutdown (device cannot be powered down). Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the DAC will cause it to exit a software shutdown state. Active-Low Chip-Select Input (Digital Input) Serial Data Input. Data is clocked in on the rising edge of SCLK. Serial Clock Input Digital Ground Serial Data Output User-Programmable Output (Digital Output) Power-Down Input (Digital Input). Pulling PD high when PDL = VDD places the IC into shutdown with a maximum shutdown current of 20A. Analog Ground Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V (MAX5130) or +1.25V (MAX5131) nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF. Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to VDD when using an external reference. Positive Power Supply. Bypass with a 0.1F capacitor in parallel with a 4.7F capacitor to AGND. FUNCTION
4
PDL
5 6 7 8 9 10 11 12 13 14
CLR CS DIN SCLK DGND DOUT UPO PD AGND REF
15 16 8
REFADJ VDD
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
CS DIN SCLK VDD AGND DGND
PDL PD
SR CONTROL
16-BIT SHIFT REGISTER
DOUT LOGIC OUTPUT UPO OS R
RSTVAL CLR 13
DECODE CONTROL 0.6384R INPUT REGISTER DAC REGISTER DAC GAIN = 1.6384X OUT
MAX5130 MAX5131
BANDGAP 1.25V REFERENCE
4k
2X (1X)
2.5V, (1.25V) REFERENCE BUFFER
( ) FOR MAX5131 ONLY
REFADJ
REF
Figure 1. Simplified Functional Block Diagram
_______________Detailed Description
The MAX5130/MAX5131 13-bit, voltage-output DACs are easily configured with a 3-wire serial interface. They include a 16-bit data-in/data-out shift register and have a double-buffered input consisting of an input register and a DAC register. In addition, these devices employ precision bandgap references and trimmed internal resistors to produce a gain of 1.6384V/V, maximizing the output voltage swing (Figure 1). The MAX5130/ MAX5131 output amplifier's offset-adjust pin allows for a DC shift in the DAC outputs. The full-scale output voltage is +4.0955V for the MAX5130 and +2.04775V for the MAX5131. These DACs are designed with an inverted R-2R ladder network (Figure 2) that produces a weighted output voltage proportional to the digital input code.
OS R
0.6384R R R R OUT
2R
2R D0
2R D10
2R D11
2R D12
REF* AGND
Internal Reference
Both the MAX5130 and MAX5131 use an on-board precision bandgap reference to generate an output voltage of +2.5V (MAX5130) or +1.25V (MAX5131). With a low temperature coefficient of only 10ppm/C (max), the REF pin can source up to 100A and may become unstable with capacitive loads exceeding 100pF. REFADJ can be used for minor adjustments (1%) to the
SHOWN FOR ALL 1s ON DAC *INTERNAL 2.5V (MAX5130) AND 1.25V (MAX5131) OR EXTERNAL REFERENCE.
Figure 2. Simplified Inverted R-2R DAC Structure
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
reference voltage. Use the circuits shown in Figure 3a (MAX5130) and Figure 3b (MAX5131) to achieve these adjustments. Connect a 33nF capacitor from REFADJ to AGND to establish low-noise operation of the DAC. Larger capacitor values may be used, but will result in increased start-up delay. The time constant () for the start-up delay is determined by the REFADJ input impedance of 4k and CREFADJ: = 4k * CREFADJ buffer gain, the MAX5131 achieves a full-scale output of +2.04775V, while the MAX5130 provides a +4.0955V full-scale output with a +2.5V reference. The output amplifier has a typical slew rate of 0.6V/s and settles to 0.5LSB within 20s, with a load of 5k in parallel with 100pF. Loads less than 1k may result in degraded performance. The OS pin may be used to adjust the output offset voltage. For instance, to achieve a +1V offset, apply -1.566V (Offset = -[Output Buffer Gain - 1] * VOS) to OS to produce an output voltage range from +1V to (1V + VREF * 1.6384V/V). Note that the DAC's output range is still limited by the maximum output voltage specification.
External Reference
An external reference may be applied to the REF pin. Disable the internal reference by pulling REFADJ to VDD. This allows an external reference signal (AC- or DC-based) to be fed into the REF pin. For proper operation, do not exceed the input voltage range limits of 0V to (VDD - 1.4V) for VREF. Determine the output voltage using the following equation (REFADJ = VDD; OS = AGND): VOUT = [VREF * (NB / 8192)] * 1.6384V/V where NB is the numeric value of the MAX5130/ MAX5131 input code (0 to 8191), VREF is the external reference voltage, and 1.6384V/V is the gain of the internal output amplifier. The REF pin has a minimum input resistance of 40k and is code-dependent.
Power-Down Mode
The MAX5130/MAX5131 feature software- and hardware-programmable (PD pin) shutdown modes that reduce the typical supply current to 3A. To enter software shutdown mode, program the control sequence for the DAC as shown in Table 1. In shutdown mode, the amplifier output becomes highimpedance and the serial interface remains active. Data in the input registers is saved, allowing the MAX5130/MAX5131 to recall the output state prior to entering shutdown when returning to normal operation mode. To exit shutdown mode, load both input and DAC registers simultaneously or update the DAC register from the input register. When returning from shutdown mode, wait 2ms for the reference to settle. When using an external reference, the DAC requires only 20s for the output to stabilize.
Output Amplifier
The output amplifier of the MAX5130/MAX5131 employs a trimmed resistor-divider to set a gain of +1.6384V/V and minimize the gain error. With its onboard laser-trimmed +1.25V reference and the output
+5V
+3V
90k 400k 100k 33nF REFADJ
MAX5130
15k 400k 100k 33nF REFADJ
MAX5131
Figure 3a. MAX5130 Reference Adjust Circuit
Figure 3b. MAX5131 Reference Adjust Circuit
10
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD FUNCTION C2 0 0 0 0 1 1 1 1 1 C1 0 0 1 1 0 0 1 1 1 C0 0 1 0 1 1 0 0 1 1 D12 ............... D0 XXXXXXXXXXXXX 13-Bit DAC Data 13-Bit DAC Data XXXXXXXXXXXXX XXXXXXXXXXXXX XXXXXXXXXXXXX XXXXXXXXXXXXX 1XXXXXXXXXXXX 00XXXXXXXXXXX No operation. Load input register; DAC register unchanged. Simultaneously load input and DAC registers; exit shutdown. Update DAC register from input register; exit shutdown. Shutdown DAC (provided PDL = 1). UPO goes low (default). UPO goes high. Mode 1; DOUT clocked out on SCLK's rising edge. Mode 0; DOUT clocked out on SCLK's falling edge (default).
X = Don't care
Power-Down Lockout Input (PDL) The power-down lockout pin (PDL) disables shutdown when low. When in shutdown mode, a high-to-low transition on PDL will wake up the DAC with its output still set to the state prior to power-down. PDL can also be used to wake up the device asynchronously. Power-Down Input (PD) Pulling PD high places the MAX5130/MAX5131 in shutdown mode. Pulling PD low will not return the MAX5130/ MAX5131 to normal operation. A high-to-low transition on PDL or appropriate commands (Table 1) via the serial interface are required to exit power-down.
DIN MOSI
VDD
SS
MAX5130 MAX5131 SCLK
SCK
SPI/QSPI PORT (PIC16/PIC17)
Serial-Interface Configuration (SPI/QSPI/MICROWIRE/PIC16/PIC17)
The MAX5130/MAX5131 3-wire serial interface is compatible with SPI, QSPI, PIC16/PIC17 (Figure 4) and MICROWIRE (Figure 5) interface standards. The 2-bytelong serial input word contains three control bits and 13 data bits in MSB-first format (Table 2). The MAX5130/MAX5131's digital inputs are double buffered, which allows the user to: * * * Load the input register without updating the DAC register, Update the DAC register with data from the input register, Update the input and DAC registers concurrently.
MAX5130 MAX5131
( ): PIC16/PIC17 ONLY
CS
I/O
CPOL = 0, CPHA = 0 (CHE = 1, CKP = 0, SMP = 0, SSPM3-SSPM0 = 0001)
Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17)
SCLK
SK MICROWIRE PORT
DIN
SO
CS
I/O
Figure 5. MICROWIRE Interface Connections
______________________________________________________________________________________ 11
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
The 16-bit input word may be sent in two 1-byte packets (SPI-, MICROWIRE- and PIC16/PIC17-compatible), with CS low during this period. The control bits C2, C1, and C0 (Table 1) determine: * The clock edge on which DOUT is to be clocked out via the serial interface, * The state of the user-programmable logic output, * The configuration of the device after shutdown. The general timing diagram in Figure 6 illustrates how data is acquired. CS must be low for the part to receive data. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. When CS transitions high, data is latched into the input and/or DAC registers, depending on the setting of the three control bits C2, C1, and C0. The maximum serial clock frequency guaranteed for proper operation is 10MHz for the MAX5130 and 6.6MHz for the MAX5131. Figure 7 depicts a more detailed timing diagram of the serial interface.
PIC16 with SSP Module and PIC17 Interface
The MAX5130/MAX5131 are compatible with a PIC16/PIC17 microcontroller (C), using the synchronous serial port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 4 and configure the PIC16/PIC17 as system master by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 3 and 4. In SPI mode, the PIC16/PIC17 Cs allow 8 bits of data to be transmitted synchronously and received simultaneously. Two consecutive 8-bit writings (Figure 6) are necessary to feed the DAC with three control bits and 13 data bits. DIN data transitions on the serial clock's falling edge and is clocked into the DAC on SCLK's rising edge. The first 8 bits on DIN contain the three control bits (C2, C1, and C0) and the first five data bits (D12-D8). The second 8-bit word contains the remaining bits (D7-D0).
Table 2. Serial Data Format
MSB ............................................................................... LSB 16 BITS OF SERIAL DATA Control Bits C2, C1, C0
CS
MSB ..... Data Bits ..... LSB D12................................D0
SCLK 1 DIN C2 C1 C0 D12 D11 D10 D9 8 D8 D7 9 D6 D5 D4 D3 D2 D1 16 D0
COMMAND EXECUTED
Figure 6. Serial-Interface Timing
tCSW CS tCS0 SCLK tCH tCP DIN tDS DOUT tDO1 tDO2 tDH tCL tCSS tCSH tCS1
Figure 7. Detailed Serial-Interface Timing
12 ______________________________________________________________________________________
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
Table 3. Detailed SSPCON Register Contents
CONTROL BIT WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX5130/MAX5131 SETTING X X 1 0 0 0 0 1 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16. SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write Collision Detection Bit Receive Overflow Detection Bit Synchronous Serial Port Enable Bit 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO and SCI as serial-port pins. Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
X = Don't care
Table 4. Detailed SSPSTAT Register Contents
CONTROL BIT SMP CKE D/A P S R/W UA BF BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 MAX5130/MAX5131 SETTINGS 0 1 X X X X X X SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT) SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer Full Status Bit
X = Don't care
Serial Data Output
The contents of the internal shift register are output serially on DOUT, allowing for daisy-chaining (see Applications Information) of multiple devices as well as data readback. The MAX5130/MAX5131 may be programmed to shift data out on DOUT on the serial clock's rising edge (Mode 1) or falling edge (Mode 0). The latter is the default during power-up and provides a lag of 16 clock cycles, maintaining SPI, QSPI, MICROWIRE, and PIC16/PIC17 compatibility. In Mode 1, the output data lags DIN by 15.5 clock cycles. During power-down, DOUT retains its last digital state prior to shutdown.
User-Programmable Output (UPO)
The UPO feature allows an external device to be controlled through the serial-interface setup (Table 1), thereby reducing the number of microcontroller I/O ports required. During power-down, this output will retain the last digital state before shutdown. With CLR pulled low, UPO will reset to the default state after wake-up.
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13
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
__________Applications Information
Definitions
Integral Nonlinearity (INL) Integral nonlinearity (Figure 8a) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every single step. Differential Nonlinearity (DNL) Differential nonlinearity (Figure 8b) is the difference between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than 1LSB, the DAC guarantees no missing codes and is monotonic.
Offset Error The offset error (Figure 8c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated for by trimming. Gain Error Gain error (Figure 8d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.
7 6 ANALOG OUTPUT VALUE (LSB) ANALOG OUTPUT VALUE (LSB) 6 5 4 3 2 1 0 000 001 010 011 100 101 110 111 DIGITAL INPUT CODE AT STEP 001 (1/4 LSB ) AT STEP 011 (1/2 LSB ) 5 4 3 1 LSB 2 1 0 000 001 010 011 100 101 DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 LSB DIFFERENTIAL LINEARITY ERROR (-1/4 LSB)
Figure 8a. Integral Nonlinearity
Figure 8b. Differential Nonlinearity
3 ANALOG OUTPUT VALUE (LSB)
ACTUAL DIAGRAM ACTUAL OFFSET POINT IDEAL DIAGRAM ANALOG OUTPUT VALUE (LSB)
7
IDEAL FULL-SCALE OUTPUT GAIN ERROR (-1 1/4 LSB)
2
6 IDEAL DIAGRAM 5 ACTUAL FULL-SCALE OUTPUT
1 OFFSET ERROR (+1 1/4 LSB)
0 000
IDEAL OFFSET POINT 001
4 0 011
010
000 100
101
110
111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 8c. Offset Error
14
Figure 8d. Gain Error
______________________________________________________________________________________
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference
Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value within the converter's specified accuracy. Digital Feedthrough Digital feedthrough is noise generated on the DAC's output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself.
MAX5130/MAX5131
+5V/+3V REF VDD
OS
MAX5130 MAX5131
DAC AGND GAIN = 1.638V/V
R 0.6384R OUT DGND
Unipolar Output
Figure 9 shows the MAX5130/MAX5131 setup for unipolar, Rail-to-Rail (R) operation with a gain of 1.6384V/V. With its +2.5V internal reference, the MAX5130 can generate a unipolar output range of 0 to +4.0955V. The MAX5131 produces a range of 0 to +2.04775V with its on-board +1.25V reference. Table 5 lists example codes for unipolar output voltages. An offset to the output voltage can be achieved by simply connecting the appropriate voltage to the OS pin, as shown in Figure 10.
Figure 9. Unipolar Output Circuit (OS = AGND) Using Internal (+1.25V/+2.5V) or External Reference. With external reference, pull REFADJ to VDD.
+5V/+3V REF REFADJ VDD OS + VOS R 0.6384R DAC AGND DGND OUT
Bipolar Output
The MAX5130/MAX5131 can be configured for unitygain bipolar operation (OS = OUT) using the circuit shown in Figure 11. The output voltage VOUT is thereby given by the following equation: VOUT = VREF * [ {G * (NB / 8192)} - 1] where NB is the numeric value of the DAC's binary input code, VREF is the voltage of the internal (or external) precision reference, and G is the overall gain. The application circuit in Figure 11 uses a low-cost operational amplifier (MAX4162) external to the MAX5130/ MAX5131 in a unity-gain configuration. This provides an overall circuit gain of 2V/V. Table 6 lists example codes for bipolar output voltages.
MAX5130 MAX5131
Figure 10. Circuit for Adding Offset to the DAC's Output
+5V/+3V REF VDD R
50k OS
50k
Reset (RSTVAL) and Clear (CLR) Functions
The MAX5130/MAX5131 DACs offer a clear pin (CLR), which resets the output to a certain value, depending upon how RSTVAL is set. RSTVAL = DGND sets the output to 0, and RSTVAL = VDD sets the output to midscale when CLR is pulled low. The CLR pin has a minimum input resistance of 40k in series with a diode to the supply voltage (VDD). If the digital voltage is higher than the supply voltage for the part, a small input current may flow, but this current will be limited to (V CLR - VDD - 0.5V) / 40k. Note: Clearing the DAC will also cause the part to exit software shutdown (PD = 0).
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. MAX5130 MAX5131
DAC
V+
0.6384R OUT DGND AGND V-
VOUT
MAX4162
Figure 11. Unity-Gain Bipolar Output Circuit Using Internal (+1.25V/+2.5V) or External Reference. With external reference, pull REFADJ to VDD.
______________________________________________________________________________________
15
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
Table 5. Unipolar Code Table (Gain = +1.6384V/V)
DAC CONTENTS MSB LSB MAX5130 1 1111 1111 1111 1 0000 0000 0001 1 0000 0000 0000 0 1111 1111 1111 0 0000 0000 0001 0 0000 0000 0000 +4.0955V +2.0485V +2.0480V +2.0475V +0.5mV 0V ANALOG OUTPUT INTERNAL REFERENCE MAX5131 +2.04775V +1.02425V +1.02400V +1.02375V +0.25mV 0V EXTERNAL REFERENCE +VREF (8191 / 8192) * 1.6384 +VREF (4097 / 8192) * 1.6384 +VREF (4096 / 8192) * 1.6384 +VREF (4095 / 8192) * 1.6384 +VREF (1 / 8192) * 1.6384 0V
Table 6. Bipolar Code Table for Figure 11
DAC CONTENTS MSB LSB MAX5130 1 1111 1111 1111 1 0000 0000 0001 1 0000 0000 0000 0 1111 1111 1111 0 0000 0000 0001 0 0000 0000 0000 +2.49939V +610.35V 0V -610.35V -2.49939V -2.5V ANALOG OUTPUT INTERNAL REFERENCE MAX5130 +1.24969V +305.18V 0V -305.18V -1.24969V -1.25V EXTERNAL REFERENCE VREF * [ {2 * (8191 / 8192)} - 1] VREF * [ {2 * (4097 / 8192)} - 1] VREF * [ {2 * (4096 / 8192)} - 1] VREF * [ {2 * (4095 / 8192)} - 1] VREF * [ {2 * (1 / 8192)} - 1] -VREF
SCLK
I
SCLK
II
SCLK
III
MAX5130 MAX5131
DIN CS DOUT DIN CS
MAX5130 MAX5131
DOUT DIN CS
MAX5130 MAX5131
DOUT
TO OTHER SERIAL DEVICES
Figure 12. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT
Daisy-Chaining Devices
Any number of MAX5130/MAX5131s can be daisychained simply by connecting the serial data output pin (DOUT) of one device to the digital input pin (DIN) of the following device in the chain (Figure 12).
Another configuration allows several MAX5130/ MAX5131 DACs to share one common DIN signal line (Figure 13). In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. However, more I/O lines are required in this configuration, because each IC needs a dedicated CS line.
16
______________________________________________________________________________________
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference
Using an External Reference with AC Components
The MAX5130/MAX5131 have multiplying capabilities within the reference input voltage range specifications. Figure 14 shows a technique for applying a sinusoidal input to REF, where the AC signal is offset before being applied to the reference input. = VDD). Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Minimize lead lengths to reduce lead inductance.
MAX5130/MAX5131
Layout Considerations
Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required.
Power-Supply and Bypassing Considerations
On power-up, the input and DAC registers are cleared to either zero (RSTVAL = DGND) or midscale (RSTVAL
DIN SCLK CS1 CS2 CS3 CS I CS II CS III TO OTHER SERIAL DEVICES
MAX5130 MAX5131
SCLK DIN SCLK DIN
MAX5130 MAX5131
DIN
MAX5130 MAX5131
SCLK
Figure 13. Multiple Devices Share One Common Digital Input (DIN)
+5V/+3V +5V/+3V
AC REFERENCE INPUT
26k
MAX495
500mVp-p 10k REF VDD R OS
0.6384R DAC OUT
AGND
MAX5130 MAX5131
DGND
Figure 14. External Reference with AC Components
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+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
___________________Chip Information
TRANSISTOR COUNT: 3308 SUBSTRATE CONNECTED TO AGND
Package Information
QSOP.EPS
18
______________________________________________________________________________________
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference
NOTES
MAX5130/MAX5131
19
______________________________________________________________________________________
+3V/+5V, 13-Bit, Serial Voltage-Output DACs with Internal Reference MAX5130/MAX5131
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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